An Efficient Implementation of Fir Filter on FPGA Using Micro Programmed Controller

Digital finite impulse response (FIR) filters play a very important role in digital signal processing (DSP) applications ranging from image and video processing to wireless communication. Digital FIR filter is primarily composed of multipliers, adders and delay elements. Several techniques have been reported in the open literature to implement digital FIR filters using Field Programmable Gate Array (FPGA). This paper also presents an FPGA implementation of FIR filter but using a novel micro programmed controller based design approach. The proposed controller controls the sequence of operation of the filter. To demonstrate the technique, design of a sequential 16-tap digital FIR filter based on the micro programmed controller is presented. The proposed FIR filter is coded in VHDL using modular design approach and implemented in Spartan-3E FPGA. Performance evaluation is done based on the implementation results obtained through Xilinx ISE tool